JPH0234457B2 - - Google Patents
Info
- Publication number
- JPH0234457B2 JPH0234457B2 JP59036679A JP3667984A JPH0234457B2 JP H0234457 B2 JPH0234457 B2 JP H0234457B2 JP 59036679 A JP59036679 A JP 59036679A JP 3667984 A JP3667984 A JP 3667984A JP H0234457 B2 JPH0234457 B2 JP H0234457B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- substrate support
- resin
- mold
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59036679A JPS60180127A (ja) | 1984-02-27 | 1984-02-27 | 樹脂封止型半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59036679A JPS60180127A (ja) | 1984-02-27 | 1984-02-27 | 樹脂封止型半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60180127A JPS60180127A (ja) | 1985-09-13 |
JPH0234457B2 true JPH0234457B2 (en]) | 1990-08-03 |
Family
ID=12476536
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59036679A Granted JPS60180127A (ja) | 1984-02-27 | 1984-02-27 | 樹脂封止型半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60180127A (en]) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2839188B2 (ja) * | 1987-06-04 | 1998-12-16 | オリンパス光学工業株式会社 | 固体撮像装置 |
US5018003A (en) * | 1988-10-20 | 1991-05-21 | Mitsubishi Denki Kabushiki Kaisha | Lead frame and semiconductor device |
JP2528505B2 (ja) * | 1988-10-24 | 1996-08-28 | ローム株式会社 | 半導体装置におけるモ―ルド部の成形装置 |
JP4728490B2 (ja) * | 2001-02-23 | 2011-07-20 | 日本インター株式会社 | 半導体装置の製造方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53118478A (en) * | 1977-03-25 | 1978-10-16 | Hitachi Ltd | Resin molded products, their manufacture, and molding tool for it |
-
1984
- 1984-02-27 JP JP59036679A patent/JPS60180127A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS60180127A (ja) | 1985-09-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5902959A (en) | Lead frame with waffled front and rear surfaces | |
US6410363B1 (en) | Semiconductor device and method of manufacturing same | |
US7834433B2 (en) | Semiconductor power device | |
JP3027512B2 (ja) | パワーmosfet | |
JP2857648B2 (ja) | 電子部品の製造方法 | |
KR960005039B1 (ko) | 수지밀봉형 반도체장치 | |
JPH0234457B2 (en]) | ||
JPH038113B2 (en]) | ||
JP3427492B2 (ja) | 凸型ヒートシンク付き半導体装置及びその凸型ヒートシンクの製造方法 | |
JP2532826B2 (ja) | 樹脂封止型半導体装置の製造方法 | |
JP4917296B2 (ja) | 半導体装置の製造方法 | |
US20190229044A1 (en) | Lead frame with plated lead tips | |
JPH04174547A (ja) | 表面実装型電力用半導体装置 | |
JPH07176664A (ja) | 半導体装置およびその製造方法 | |
JPH0234456B2 (en]) | ||
JPS6223097Y2 (en]) | ||
JP3528711B2 (ja) | リードフレームとそれを用いた樹脂封止型半導体装置およびその製造方法 | |
JPH01133329A (ja) | 樹脂封止型半導体装置の製造方法 | |
JPH0870087A (ja) | リードフレーム | |
JPS62120035A (ja) | 樹脂封止型半導体装置の製造方法 | |
JPS638618B2 (en]) | ||
KR200164521Y1 (ko) | 티엘형 반도체 패키지 | |
JPH01105550A (ja) | 樹脂封止型半導体装置の製造方法 | |
KR100575859B1 (ko) | 볼 그리드 어레이 패키지 | |
JPS6193654A (ja) | 樹脂封止型半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |